Electrostatic discharge power clamp with fail-safe design

A method of fabricating an electrostatic discharge protection circuit for a chip, the method comprising:

• forming, using a substrate, a first resistor and a first capacitor of a first timing circuit;
• forming, using the substrate, a second resistor and a second capacitor of a second timing circuit;
• forming, using the substrate, a power clamp device;
• and
• forming, using the substrate, a logic gate including a first input coupled with a first node coupling the first capacitor with the first resistor, a second input coupled with a second node between the second capacitor and the second resistor, and an output coupled with the power clamp device,
• wherein the first capacitor and the second capacitor each comprise at least one deep trench capacitor.

A method of operating an electrostatic discharge protection circuit when power is applied to a chip and the electrostatic discharge protection circuit on the chip, the method comprising:

• supplying a first voltage to a first input of a logic gate from a first node between a first resistor and a first capacitor of a first timing circuit;
• supplying a second voltage to a second input of the logic gate from a second node between a second resistor and a second capacitor of a second timing circuit;
• and
• outputting a third voltage from the logic gate to a power clamp device based on the first voltage and the second voltage,
• wherein the third voltage places the power clamp device in a high-impedance state, and the first capacitor and the second capacitor are each deep trench capacitors.

An electrostatic discharge protection circuit comprising:

• a power clamp device;
• a timing circuit including a resistor, a first capacitor that is coupled with the resistor at a node, and a second capacitor that is coupled with the resistor at the node;
• a first field-effect transistor including a first gate, the first field-effect transistor coupled in series with the first capacitor between a positive rail of a power supply and a negative rail of the power supply;
• and
• a decoder including a first output line coupled with the first gate, the decoder configured to selectively output a first voltage on the first output line to the first gate.