Stacked capacitor with enhanced capacitance and method of manufacturing the same

A semiconductor device, comprising:

• a semiconductor substrate;
• and
• a stacked capacitor over the semiconductor substrate, the stacked capacitor comprising:
• a lower electrode plate over the semiconductor substrate;
• an upper electrode plate over the lower electrode plate;
• an intermediate electrode plate between the lower electrode plate and the upper electrode plate;
• a first dielectric layer between the lower electrode plate and the intermediate electrode plate;
• a second dielectric layer between the intermediate electrode plate and the upper electrode plate;
• a cap layer over the upper electrode plate;
• a first via hole through the cap layer, the upper electrode plate, the second dielectric layer, the intermediate electrode plate and the first dielectric layer, partially exposing the lower electrode plate;
• a second via hole through the cap layer, the upper electrode plate and the second dielectric layer, partially exposing the intermediate electrode plate;
• a third via hole through the cap layer, partially exposing the upper electrode plate;
• a first contact via in the first via hole and electrically connected to the lower electrode plate, wherein a bottom of the first contact via stops at an upper surface of the lower electrode plate;
• a second contact via in the second via hole and electrically connected to the intermediate electrode plate, wherein a bottom of the second contact via stops at an upper surface of the intermediate electrode plate;
• and
• a third contact via in the third via hole and electrically connected to the upper electrode plate, wherein a bottom of the third contact via stops at an upper surface of the upper electrode plate.

A method of manufacturing a semiconductor device, comprising:

• forming, in an order of, a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, a third conductive layer and a cap layer over a semiconductor substrate;
• and
• forming a first via hole extending through the cap layer, the third conductive layer, the second dielectric layer, the second conductive layer and the first dielectric layer to expose the first conductive layer, a second via hole extending through the cap layer, the third conductive layer and the second dielectric layer to expose the second conductive layer, and a third via hole extending through the cap layer to expose the third conductive layer,
• wherein forming the first via hole, the second via hole and the third via hole comprises:
• forming the second via hole and a recess partially exposing the second conductive layer;
• blocking the second via hole;
• forming the third via hole through the recess;
• and
• forming the first via hole.