Stacked type semiconductor memory device and method for manufacturing the same

A semiconductor memory device, comprising:

• a stacked body including a plurality of insulating films and a plurality of electrode films, each of the plurality of insulating films and each of the plurality of electrode films being stacked alternately along a first direction, a configuration of an end portion of the stacked body in a second direction being a stairstep configuration, the second direction being orthogonal to the first direction, a step being formed in the stairstep configuration for each of the electrode films;
• a plurality of first semiconductor pillars disposed in a first region of the stacked body where the steps are not formed, the plurality of first semiconductor pillars extending in the first direction and piercing the stacked body;
• a first memory film formed between one of the first semiconductor pillars and one of the electrode films;
• a plurality of second semiconductor pillars disposed in a second region of the stacked body where the steps are formed, the plurality of second semiconductor pillars extending in the first direction and piercing the stacked body;
• and
• a contact disposed on the electrode film and connected to the electrode film for each of the steps,
• when viewed from the first direction, the plurality of first semiconductor pillars and the plurality of second semiconductor pillars being disposed at some of lattice points of a lattice, the lattice being made of first imaginary straight lines extending in a third direction and second imaginary straight lines extending in a fourth direction intersecting the third direction, an arrangement period of the lattice points in the first region where the plurality of first semiconductor pillars are disposed at some of the lattice points being equal to an arrangement period of the lattice points in the second region where the plurality of second semiconductor pillars are disposed at some of the lattice points, the contact being disposed at a position including other of the lattice points, the second semiconductor pillars not being disposed at the lattice points included in the contact, plural pillars of the plurality of second semiconductor pillars being disposed at each of the steps along at least one of the third direction and the fourth direction.