Si recess method in HKMG replacement gate technology

An integrated circuit, comprising:

• a substrate including a periphery region having a first substrate surface and a memory cell region having a second substrate surface, wherein the second substrate surface is recessed within the substrate relative to the first substrate surface;
• a logic transistor disposed on the first substrate surface and including a logic gate electrode separated from the first surface by a logic gate dielectric;
• and
• a memory cell disposed on the second substrate surface and including a memory gate electrode separated from the second substrate surface by a memory gate dielectric, wherein a top surface of the logic gate electrode is co-planar with a top surface of the memory gate electrode.

An integrated circuit, comprising:

• a substrate including a first region having a first substrate surface and a second region having a second substrate surface, wherein the second substrate surface is recessed within the substrate relative to the first substrate surface;
• a first transistor disposed on the first substrate surface and including a first gate electrode separated from the first substrate surface by a first gate dielectric;
• and
• a second transistor disposed on the second substrate surface and including a second gate electrode separated from the second substrate surface by a second gate dielectric, wherein a top surface of the first gate electrode is co-planar with a top surface of the second gate electrode.