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US 9,853,013 B2Granted
Semiconductor device having stacked chips
AssigneeToshiba Memory Corporation
InventorMasaru Koyanagi
Life of this patent
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Abstract
According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, wherein these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, and includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.
Claims10
A semiconductor device comprising:
- a first chip having a first via and a second via through the first chip;
- and
- a second chip provided on the first chip and having a third via and a fourth via through the second chip;
- wherein the first chip includes:
- a first inversion circuit, the first inversion circuit being configured to invert a first address signal to an first inverted address signal and supply the first inverted address signal to the second chip through the first via;
- a first logical operation circuit connected to the first inversion circuit, the first logical operation circuit being configured to perform a logical operation on a second address signal and the first inverted address signal, and supply a first arithmetic operation output signal to the second chip through the second via;
- and
- a first selection circuit connected to the first logical operation circuit, the first selection circuit being configured to select a chip based on at least the first arithmetic operation output signal.
5 more elements
A semiconductor device, comprising:
- a package substrate having a first pad and a second pad on a first surface;
- an I/F chip provided on the first surface of the package substrate, the I/F chip having a second surface and a third surface, the second surface facing the first surface, the I/F chip having a third pad and a fourth pad on the third surface, the third pad being connected to the first pad, and the second pad being connected to the fourth pad;
- and
- a plurality of stacked chips provided on the I/F chip,
- wherein:
- the plurality of stacked chips include a first chip and a second chip, each of the first and second chips including a first via, a second via, a third via, a fourth via, a first circuit, a second circuit, and a third circuit,
- the first via of the first chip is connected to the first circuit of the first chip,
- the first via of the second chip is connected to the first circuit of the second chip,
- the first via of the first chip is connected the first via of the second chip,
- the second via of the first chip is connected to the second via of the second chip through the second circuit of the second chip,
- the third via of the first chip is connected to the third via of the second chip,
- the fourth via of the first chip is connected to the fourth via of the second chip,
- the third circuit of the second chip is connected to the third and fourth vias of the first chip,
- the third pad of the I/F chip is connected to the first via and the second via of the first chip through a fourth circuit in the I/F chip, and
- the fourth pad of the I/F circuit is connected to the third via and the fourth via of each of the first chip through a fifth circuit in the I/F chip.
12 more elements
Dependencies are inferred from the claim text.