Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device, the method comprising:

• determining a TSV candidate region in each of a plurality of dies, wherein each of the TSV candidate regions is a region available in each of the plurality of dies for connection to through silicon vias (TSVs);
• determining a bound region for each of a plurality of nets, wherein each of the nets includes the pins which are to be electrically connected in common to one of the TSVs, and each of the bound regions is a region encompassing a projection of locations of the pins constituting a respective one of the nets;
• calculating areas of overlap, as viewed in plan, between the bound region and the TSV candidate regions, respectively, for each of the nets;
• determining a routing order of the nets based on the areas of overlap calculated for the nets;
• routing the pins of the nets with the TSVs in the routing order;
• and
• fabricating a 3D integrated circuit having a stack of dies including pins, and TSVs electrically connecting respective ones of the dies to each other and to which the pins are electrically connected in conformance with the routing order.

A method of manufacturing a semiconductor device, the method comprising:

• determining N TSV candidate regions for N dies having a plurality of pins and stacked in a vertical direction, where N is an integer greater than or equal to 2;
• determining a first bound region horizontally encompassing locations of pins of a first net and a second bound region horizontally encompassing pins of a second net;
• calculating a first area by summing all areas of overlap, as viewed in plan, between the first bound region and the N TSV candidate regions, and assigning the first area to the first net;
• calculating a second area by summing all areas of overlap, as viewed in plan, between the second bound region and the N TSV candidate regions, and assigning the second area to the second net;
• routing the nets with TSVs in an order based on their assigned areas;
• and
• fabricating a 3D integrated circuit having a stack of dies including pins, and TSVs electrically connecting respective ones of the dies to each other and to which the pins are electrically connected in conformance with the routing order.