Folded divider architecture
AssigneeSTMicroelectronics Asia Pacific Pte Ltd
InventorBeng-Heng Goh
Life of this patent
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Abstract
A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.
Claims14
A circuit, comprising:
- a counter circuit comprising:
- a counter for a clock divider configured to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal, wherein the divider value is a value that the clock signal is to be divided by;
- a logic circuit configured to
- compare a value contained in the divider counter to a reference value and to generate an end count signal as a function of the value contained in the divider counter matching the reference value, and
- transition a toggle signal at a same edge of each pulse of the end count signal,
- wherein the counter for the clock divider is also configured to be reloaded with the most significant bits of the divider value as a function of the end count signal;
- and
- wherein the clock divider is configured to generate a divided version of the clock signal as a function of the toggle signal.
A method, comprising:
- loading a counter for a clock divider with most significant bits of a divider value, and decrementing the counter at a same edge of each pulse of a clock signal,
- comparing a value contained in the divider counter to a reference value and generating an end count signal as a function of the value contained in the divider counter matching the reference value;
- transitioning a toggle signal at a same edge of each pulse of the end count signal;
- reloading the counter for the clock divider with the most significant bits of the divider value as a function of the end count signal;
- and
- generating a divided version of the clock signal as a function of the toggle signal.
Dependencies are inferred from the claim text.