Extensible time space switch systems and methods

A pipelined time-space switch, comprising:

• input circuitry comprising N input links each receiving M timeslots, wherein N and M are integers;
• a two-dimensional matrix of a plurality of time-space switches, wherein the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N input links in a pipelined manner where each of the plurality of time-space switches interconnect to adjacent neighbors only;
• and
• output circuitry comprising N output links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix;
• wherein the input circuitry is located orthogonal to the output circuitry and each of the input circuitry and the output circuitry are adjacent to the two-dimensional matrix;
• and
• wherein input data flows from the input circuitry orthogonal to the output circuitry, and wherein output data and control flows to the output circuitry orthogonal to the input circuitry;
• and
• common control circuitry parallel to the input circuitry, wherein the common control circuitry is communicatively coupled to separate configuration memories for each of the N output links parallel to the output circuitry, wherein the configuration memories are configured to control the data flow to the output circuitry for their respective links, wherein the configuration memories are directly coupled to a first column of the plurality of time-space switches and not directly coupled to other columns of the plurality of time-space switches, wherein addressing from the configuration memories is pipelined through the two-dimensional matrix, and wherein the common control circuitry, for providing launch signals with the addressing to the two-dimensional matrix, is connected to the input circuitry and the configuration memories,
• wherein the input circuitry comprises input framers for each of the N input links;
• wherein the output circuitry comprises output framers for each of the N output links;
• and wherein the input framers and the output framers utilize efficient line coding relative to 8B10B, comprising of SLP112 timeslot data framing, 64B65B encoding, Fire code forward error correction and scrambling.

A pipelined time-space switching method, comprising:

• receiving M timeslots over each of N input links, N and M are integers;
• loading each of the M timeslots for each of the N input links in a two-dimensional matrix in a pipelined fashion where interconnections in the two-dimensional matrix are only between adjacent neighbors only;
• reading out any of the M timeslots from any of the N output links from the two-dimensional matrix;
• wherein input circuitry receiving the M timeslots is located orthogonal to output circuitry reading out the any of the M timeslots and each of the input circuitry and the output circuitry are adjacent to the two-dimensional matrix;
• and
• providing common control circuitry parallel to the input circuitry, wherein the common control circuitry is communicatively coupled to separate configuration memories for each of the N output links parallel to the output circuitry, wherein the configuration memories are configured to control the data flow to the output circuitry for their respective links, wherein the configuration memories are directly coupled to a first column of the two-dimensional matrix and not directly coupled to other columns of the two-dimensional matrix, wherein addressing from the configuration memories is pipelined through the two-dimensional matrix, and wherein the common control circuitry, is connected to the input circuitry and the configuration memories,
• wherein the input circuitry and the output circuitry respectively comprise input framers and output framers which utilize efficient line coding relative to 8B10B, comprising of SLP112 timeslot data framing, 64B65B encoding, Fire code forward error correction, and scrambling.