Bypass FIFO for multiple virtual channels
AssigneeCavium, Inc.
InventorSteven C. Barner
Life of this patent
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Abstract
A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage location. The super-FIFO may enable a push to (or a pop from) every low-level FIFO, simultaneously. The super-FIFO may enable a virtual channel (VC) to use the super-FIFO, bypassing a VC FIFO for the VC, removing several cycles of latency otherwise needed for enqueuing and dequeuing messages in the VC FIFO. In addition, the super-FIFO may enable bypassing of an arbiter, further reducing latency by avoiding a penalty of the arbiter.
Claims41
A circuit with a First-In/First-Out (FIFO) property, the circuit comprising:
- a super-FIFO including a plurality of super-FIFO storage locations, the super-FIFO having a super-FIFO head pointer, a super-FIFO tail pointer, and a circular order;
- and
- wherein a plurality of low-level FIFOs, each low-level FIFO having respective head and tail pointers separate from the super-FIFO head and tail pointers, are employed as the plurality of super-FIFO storage locations to form the super-FIFO, the super-FIFO enabling a push to each low-level FIFO, simultaneously, based on the super-FIFO tail pointer and the circular order, and the super-FIFO enabling a pop from each low-level FIFO, simultaneously, based on the super-FIFO tail pointer and the circular order, to effectuate the FIFO property of the circuit.
A system comprising:
- a bypass First-In First-Out (FIFO) stage including:
- a super-FIFO including a plurality of super-FIFO storage locations, the super-FIFO having a super-FIFO head pointer and a super-FIFO tail pointer,
- wherein a plurality of low-level FIFOs, each low-level FIFO having respective head and tail pointers separate from the super-FIFO head and tail pointers, are employed as the plurality of super-FIFO storage locations to form the super-FIFO;
- and
- at least one other stage, the bypass FIFO stage enabling bypass of at least one element in the at least one other stage to reduce latency in the system.
Dependencies are inferred from the claim text.