Landing pad in peripheral circuit for magnetic random access memory (MRAM)
AssigneeAvalanche Technology, Inc.
InventorsKimihiro Satoh, Yiming Huai
Life of this patent
Estimating the term…
Loading patent…
AssigneeAvalanche Technology, Inc.
InventorsKimihiro Satoh, Yiming Huai
Estimating the term…
The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.
A memory device including:
A memory device comprising:
A memory device comprising:
A memory device including:
Dependencies are inferred from the claim text.