Programming of non-volatile memory subjected to high temperature exposure
AssigneeAvalanche Technology, Inc.
InventorsEbrahim Abedifard, Uday Chandrasekhar, Rajiv Yadav Ranjan, Yiming Huai
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AssigneeAvalanche Technology, Inc.
InventorsEbrahim Abedifard, Uday Chandrasekhar, Rajiv Yadav Ranjan, Yiming Huai
Estimating the term…
A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (MTJs) whose resistance is switchable; and a one-time-programmable (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed. Each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof. The second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.
A method for using a non-volatile memory including a plurality of magnetic tunnel junctions (MTJs) for data storage, the method comprising the steps of:
Dependencies are inferred from the claim text.
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About 9 years 11 months of term left · ends 14 Sep 2036 (estimated)
Field of the Invention
The present invention relates to a non-volatile memory, and more particularly to a magnetic random access memory (MRAM) and a method for programming the same memory subjected to high temperature exposure.
Description of the Prior Art
FIG. 1 shows a graph 10 of the resistance distributions of a population of MTJs being built during manufacturing using current manufacturing techniques.
FIGS. 2a-2d show various graphs of resistance distribution curves in accordance with embodiments and methods of the present invention.
FIG. 3 shows an exemplary memory device 30 including Blocks 0-N after sorting of a wafer onto which the memory device is formed.
In the following description of the embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration of the specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized because structural changes may be made without departing from the scope of the present invention. It should be noted that the figures discussed herein are not drawn to scale and thicknesses of lines are not indicative of actual sizes.
Methods of the invention not only retain the resistance states of a portion of a memory device with non-volatile memory cells. In accordance with a method of the invention, one or more non-volatile memory cells in a selected portion of the memory device is shorted by applying a breakdown voltage (VBreakDown) thereto, the VBreakDown being a voltage required to permanently short the non-volatile memory cells of the memory device. The shorted memory cells in the selected portion of the memory device are in a low resistance state that represents one of two logical states (“0” or “1”), while other memory cells in the selected portion are in higher resistance states, which collectively represent the other one of two logical states.
Alternatively, upon reprogramming or updating of the non-volatile memory cells of the selected portion of the memory device, programming or updating is directed to a location of the memory device other than the location of the selected portion of non-volatile memory cells within the memory device.