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US 9,792,172 B2Granted
Memory system and method of controlling nonvolatile memory
AssigneeToshiba Memory Corporation
InventorShinichi Kanno
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AssigneeToshiba Memory Corporation
InventorShinichi Kanno
Estimating the term…
According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written.
A memory system comprising:
A memory system comprising:
A method of controlling a nonvolatile memory, the method comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's: in individual solid state devices
In individual solid state devices: using codes or arrangements adapted for a specific type of error
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words:…
Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise: specific encoding…
About 9 years 1 month of term left · ends 23 Nov 2035 (estimated)
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-145713, filed Jul. 23, 2015, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to technology of controlling a nonvolatile memory.
Recently, memory systems comprising nonvolatile memories have become widespread.
FIG. 1 is a block diagram showing a configuration example of a memory system according to one embodiment.
FIG. 2 is an illustration for describing the relationship between an ordinary hierarchical storage system and a non-hierarchical storage system.
FIG. 3 is an illustration for describing a plurality of tiers which are set within the memory system of the embodiment.
In general, according to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written.
First, referring to FIG. 1, a configuration of an information processing system 1 including a memory system according to one embodiment will be described.
This memory system is a semiconductor storage device configured to write data to a nonvolatile memory, and read data from the nonvolatile memory. The memory system is realized as, for example, a NAND-flash solid-state drive (SSD) 3.