Preventing timing violations

Apparatus, comprising

• a clock adapted to provide a clock signal, wherein the clock signal alternates with a cycle between a first level and a second level different from the first level if a timing violation is not detected;
• a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level and is closed for the first signal when the clock is at the second level;
• a second combinational logic adapted to output a second signal based on the first signal passed through the first latch;
• a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level and is closed for the second signal when the clock is at the first level;
• a detecting means adapted to detect the timing violation of at least one of the first signal at the first latch when the clock signal is at the first level and of the second signal at the second latch when the clock signal is at the second level;
• a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay compared to a time of alternating between the first level and the second level according to the cycle;
• a first combinational logic adapted to output the first signal, wherein the second combinational logic is adapted to output the second signal at a second output,
• an input latch adapted to be clocked such that it passes an input signal when the clock is at the second level;
• wherein the first combinational logic is adapted to output the first signal based on the input signal passed through the input latch;
• wherein the detecting means is adapted to detect the timing violation of the second signal at the second latch when the clock is at the second level;
• wherein the first latch is not operatively connected to a means for detecting the timing violation of the first signal at the first latch when the clock is at the first level;
• wherein the first combinational logic is slow such that, if a first sampling signal is input into the first combinational logic if the clock alternates from the second level to the first level, the timing violation of the first signal based on the first sampling signal frequently occurs at the second latch;
• and
• wherein the second combinational logic is fast such that, if a second sampling signal is input into the second combinational logic if the clock alternates from the first level to the second level, the second combinational logic provides the second signal before the clock alternates to the first level with a probability of more than 50%.

Method, comprising

• passing a first signal through a first latch when a clock signal is at a first level;
• closing the first latch for the first signal when the clock signal is at a second level;
• outputting a second signal based on the first signal passed through the first latch;
• passing the second signal through a second latch when the clock signal is at the second level;
• closing the second latch for the second signal when the clock signal is at the first level;
• clocking the first latch such that the first latch is closed for the first signal when the clock is at the second level;
• clocking the second latch such that the second latch is closed for the second signal when the clock is at the first level;
• wherein the first latch and the second latch are collectively clocked, and wherein the clock signal for the first and the second latches is synchronized;
• detecting a timing violation of at least one of the first signal at the first latch when the clock signal is at the first level and the second signal at the second latch when the clock is at the second level;
• and
• stretching, if the timing violation is detected, the clock collectively for both the first latch and the second latch such that the clock alternates between the first level and the second level with a delay compared to a time of alternating between the first level and the second level according to a cycle;
• wherein the clock signal alternates with the cycle between the first level and the second level different from the first level if the timing violation is not detected.

A computer program product comprising a set of instructions stored on a non-transitory computer-readable medium which, when executed on an apparatus, is configured to cause the apparatus to:

• pass a first signal through a first latch when a clock signal is at a first level;
• close the first latch for the first signal when the clock signal is at a second level;
• output a second signal based on the first signal passed through the first latch;
• pass the second signal through a second latch when the clock signal is at the second level;
• close the second latch for the second signal when the clock signal is at the first level;
• clock the first latch such that the first latch is closed for the first signal when the clock is at the second level;
• clock the second latch such that the second latch is closed for the second signal when the clock is at the first level;
• wherein the first latch and the second latch are collectively clocked, and wherein the clock signal for the first and the second latches is synchronized;
• detect a timing violation of at least one of the first signal at the first latch when the clock signal is at the first level and the second signal at the second latch when the clock is at the second level;
• and
• stretch, if the timing violation is detected, the clock collectively for both the first latch and the second latch such that the clock alternates between the first level and the second level with a delay compared to a time of alternating between the first level and the second level according to a cycle;
• wherein the clock signal alternates with the cycle between the first level and the second level different from the first level if the timing violation is not detected.