NMOS regulated voltage reference
AssigneeHGST, Inc.
InventorsR. Jacob Baker, Ward Parkinson
Life of this patent
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Abstract
A method and system for generating a reference voltage are disclosed. The reference voltage is generated by generating a voltage VRIGHT using a first transistor and generating a voltage VBIAS using a second transistor. The gates of the two transistors are connected to a common node VREF, but the loads of the transistors have different resistances. At least one differential pair is used to detect a difference between voltages VRIGHT and VBIAS. VREF is forced to a value at which the source-drain currents in each of the transistors is equal. The transistors sued are NMOS transistors.
Claims8
A system for generating a reference voltage, the system comprising only NMOS transistors or resistors and capacitors:
- a first transistor for generating a voltage VRIGHT on its source and having a first load;
- a second transistor for generating a voltage VBIAS on its source and having a second load, wherein the gates of the first and second transistor are connected to a common node VREF, and wherein the first and second loads comprise different resistances;
- and
- at least one differential pair for detecting a difference between voltages VRIGHT and VBIAS and generating a signal related to the difference, wherein the signal related to the difference is connected to VREF, thereby forcing VREF to a value at which the source-drain currents in each of the first and second transistors are equal and wherein all the transistors are NMOS.
A method for generating a reference voltage using only NMOS transistors or resistors and capacitors, the method comprising:
- generating a voltage VRIGHT using a first transistor having a first load;
- generating a voltage VBIAS using a second transistor having a second load, wherein the gates of the first and second transistor are connected to a common node VREF, and wherein the first and second loads comprise different resistances;
- detecting a difference between the voltages VRIGHT and VBIAS using at least one differential pair and generating a single related to the difference;
- and
- forcing VREF to a value at which the source-drain currents in each of the first and second transistors are equal using only NMOS transistors.
Dependencies are inferred from the claim text.