Low-power low-dropout voltage regulators with high power supply rejection and fast settling performance

A method for providing a low-power low-dropout (LDO) voltage regulator, the method comprising:

• configuring an error amplifier to compare a sampled portion of a regulated output voltage of the LDO voltage regulator with a reference voltage and to generate an error signal at a single-ended output node of the error amplifier;
• coupling a level-shifter circuit comprising a source follower including a PMOS transistor to the error amplifier;
• coupling a fast loop comprising a current mirror and a gain boosting circuit to the level-shifter circuit and configuring the fast loop to improve a transient response-time and a slew rate of the LDO voltage regulator;
• and
• configuring an NMOS pass transistor to provide the regulated output voltage with low dropout operation;
• and
• configuring the level-shifter circuit to shift a voltage level of the error signal at the single-ended output node of the error amplifier to facilitate the low dropout operation of the NMOS pass transistor, wherein a gate terminal of the NMOS pass transistor is connected to an output node of the source follower.

A communication device, comprising:

• a low-power low-dropout (LDO) voltage regulator device comprising:
• an error amplifier configured to generate an error signal at a single-ended output node of the error amplifier based on a comparison between a sampled portion of a regulated output voltage of the LDO voltage regulator and a reference voltage;
• an NMOS pass transistor configured to provide the regulated output voltage with low dropout operation;
• a level-shifter circuit coupled to the error amplifier and the NMOS pass transistor and configured to shift a voltage level of the error signal at the single-ended output node of the error amplifier to facilitate the low dropout operation of the NMOS pass transistor, wherein the level-shifter circuit comprises a source follower including a PMOS transistor, and wherein a gate terminal of the NMOS pass transistor is connected to an output node of the source follower;
• and
• a fast loop comprising a current mirror and a gain boosting circuit coupled to the level-shifter circuit and configured to improve a transient response-time and a slew rate of the LDO voltage regulator device.