Scan flip-flop and scan test circuit including the same

A scan flip-flop comprising:

• an input unit configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode;
• and
• a flip-flop configured to latch the internal signal according to a clock signal, the flip-flop including a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other,
• wherein the flip-flop comprises a master latch including the first and second tri-state inverters, and a slave latch connected to the master latch, and
• wherein the master latch further comprises a reset switch connected between the first output node and a ground terminal, the reset switch being controlled according to a reset control signal.

A scan test circuit comprising:

• a sequential circuit unit configured to include first and second scan flip-flops, at least one of the first and second scan flip-flops including a flip-flop that includes a cross coupled structure including first and second tri-state inverters which share a first output node;
• and
• a combinational circuit unit configured to include first and second combinational logic circuits, the first combinational logic circuit supplying a first data input signal, generated by performing a logic operation on pieces of data, to the first scan flip-flop, and the second combinational logic circuit supplying a second data input signal, generated by performing a logic operation on an output signal of the first scan flip-flop, to the second scan flip-flop,
• wherein the first tri-state inverter receives a first input signal and first and second control signals, and the second tri-state inverter receives a second input signal and the first and second control signals,
• wherein the cross couple structure includes first and second active regions and a dummy region interposed between the first and second active regions in a layout view of the cross coupled structure, and first and second conductive lines extending in parallel across the first and second active regions and the dummy region,
• wherein the cross coupled structure further includes a cutout region in the dummy region for separating the first conductive line into a first portion and a second portion, and for separating the second conductive line into a third portion and a fourth portion, and
• wherein the cross couple structure further includes a diagonal contact which traverses the cutout region and connects the first portion of the first conductive line and the fourth portion of the second conductive line, and a via for applying one of the first and second control signals to the diagonal contact.

A data processing apparatus comprising:

• a logic circuit;
• and
• a scan logic group comprising a plurality of scan flip-flops each receiving input data and scan data from the logic circuit, and each selecting and outputting the received input data or the received scan data to the logic circuit, at least one of the plurality of scan flip-flops including a flip-flop that includes a cross coupled structure including first and second tri-state inverters which share a first output node, the first tri-state inverter receiving a first input signal and first and second control signals, and the second tri-state inverter receiving a second input signal and the first and second control signals,
• wherein the cross couple structure includes first and second active regions and a dummy region interposed between the first and second active regions in a layout view of the cross coupled structure, and first and second conductive lines extending in parallel across the first and second active regions and the dummy region,
• wherein the cross coupled structure further includes a cutout region in the dummy region for separating the first conductive line into a first portion and a second portion, and for separating the second conductive line into a third portion and a fourth portion, and
• wherein the cross couple structure further includes a diagonal contact which traverses the cutout region and connects the first portion of the first conductive line and the fourth portion of the second conductive line, and a via for applying one of the first and second control signals to the diagonal contact.