Tap dual port router circuitry with gated shiftDR and clockDR

An integrated circuit comprising:

• (a) a test data in lead, a test clock lead, a test mode select lead, a test data out lead, and a capture lead;
• (b) a TAP state machine having a clock input coupled to the test clock lead, a mode input coupled to the test mode select lead, data register control outputs that include a ClockDR signal and a ShiftDR signal, and instruction register control outputs;
• (c) an instruction register having a test data input coupled to the test data in lead, instruction register control inputs coupled to the instruction register control outputs, and instruction register outputs;
• (d) data registers having test data inputs coupled to the test data in lead, data register control inputs, and instruction register control inputs coupled to the instruction register outputs;
• and
• (e) dual port router circuitry having:
• (i) first multiplexer circuitry having an input connected to the capture lead, an input connected to the ShiftDR signal, a control input connected to one of the instruction register outputs, and an output;
• (ii) first gating circuitry having an input connected to the output of the multiplexer circuitry, an input connected to the control input of the first multiplexer circuitry, and a gated ShiftDR signal output coupled to a data register control input of the data registers.