Self-limiting selective epitaxy process for preventing merger of semiconductor fins

A method of forming a semiconductor structure comprising:

• providing at least one semiconductor fin including a first single crystalline semiconductor material on a substrate;
• growing a plurality of faceted semiconductor material portions including a second single crystalline semiconductor material on semiconductor surfaces of said at least one semiconductor fin by flowing at least one reactant precursor for said second single crystalline semiconductor material and an etchant in a selective epitaxy process performed in a process chamber for a duration of time, wherein a flow rate of said at least one reactant precursor and a flow rate of said etchant are selected to provide a set of crystallographically equivalent orientations in which a net deposition rate of said second single crystalline semiconductor material is either zero or negative thereby growth of said plurality of faceted semiconductor material portions stops when all of physically exposed surfaces of said plurality of faceted semiconductor material portions become faceted surfaces having crystallographically equivalent orientations within said set of crystallographically equivalent orientations;
• forming a contact-level dielectric material surrounding each semiconductor fin and in direct contact with a bottom portion of said faceted semiconductor material portions, wherein said contact-level dielectric material has contact openings;
• forming a metal semiconductor alloy portion within said contact openings and directly on an upper surface of said faceted semiconductor material portions, wherein a bottom surface and a top surface of said metal semiconductor alloy portion are faceted;
• and
• forming a contact via structure directly on said faceted upper surface of metal alloy portion, wherein outermost vertical sidewalls of said metal semiconductor alloy portion are vertically aligned with outermost vertical sidewalls of said contact via structure.