Efficient memory bandwidth utilization in a network device
AssigneeBroadcom Corporation
InventorsDavid Wu, Darren Duane Neuman, Flaviu Dorin Turean, Rajesh Shankarrao Mamidwar, Anand Tongle, Predrag Kostic
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AssigneeBroadcom Corporation
InventorsDavid Wu, Darren Duane Neuman, Flaviu Dorin Turean, Rajesh Shankarrao Mamidwar, Anand Tongle, Predrag Kostic
Estimating the term…
A system for efficient memory bandwidth utilization may include a depacketizer, a packetizer, and a processor core. The depacketizer may generate header information items from received packets, where the header information items include sufficient information for the processor core to process the packets without accessing the payloads from off-chip memory. The depacketizer may accumulate multiple payloads and may write the multiple payloads to the off-chip memory in a single memory transaction when a threshold amount of the payloads have been accumulated. The processor core may receive the header information items and may generate a single descriptor for accessing multiple payloads corresponding to the header information items from the off-chip memory. The packetizer may generate a header for each payload based at least on on-chip information and without accessing off-chip memory. Thus, the subject system provides efficient memory bandwidth utilization, e.g. at least by reducing the number of off-chip memory accesses.
A network traffic processor comprising:
A method comprising:
A computer program product comprising instructions stored in a non-transitory computer-readable storage medium, the instructions comprising:
Dependencies are inferred from the claim text.