Synthesizer module, RF transceiver and method therefor
AssigneeMediaTek Singapore Pte. Ltd.
InventorNandigam Venkata Murali
Life of this patent
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Abstract
A synthesizer module arranged to generate a timing signal. The synthesizer module comprises an odd-numbered frequency divider circuit arranged to receive a reference timing signal and to output at least one frequency-divided signal having a frequency equal to 1/M times the frequency of the reference timing signal, where M is an odd-numbered integer. A 90° phase-shift component is arranged to receive the reference timing signal and to output a 90° phase-shifted form of the reference timing signal. A re-timing circuit is arranged to re-time a set of transitions of the frequency-divided signal to be temporally aligned to transitions of the 90° phase-shifted form of the reference timing signal to generate the timing signal comprising the re-timed transitions of the frequency-divided signal.
Claims20
A synthesizer module arranged to generate at least one timing signal;
- the synthesizer module comprising:
- at least one odd-numbered frequency divider circuit arranged to receive a reference timing signal and to output at least one frequency-divided signal having a frequency equal to 1/M times the frequency of the reference timing signal, where M is an odd-numbered integer greater than 1;
- a 90° phase-shift circuit arranged to receive the reference timing signal and to output a 90° phase-shifted form of the reference timing signal;
- and
- a re-timing circuit arranged to:
- receive the at least one frequency-divided signal;
- receive the 90° phase-shifted form of the reference timing signal;
- and
- re-time a set of transitions of the frequency-divided signal to be temporally aligned to transitions of the 90° phase-shifted form of the reference timing signal to generate the at least one timing signal comprising the re-timed transitions of the frequency-divided signal.
A radio frequency transceiver module comprising at least one synthesizer module arranged to generate at least one timing signal;
- the at least one synthesizer module comprising:
- at least one odd-numbered frequency divider circuit arranged to receive a reference timing signal and to output at least one frequency-divided signal having a frequency equal to 1/M times the frequency of the reference timing signal, where M is an odd-numbered integer greater than 1;
- a 90° phase-shift circuit arranged to receive the reference timing signal and to output a 90° phase-shifted form of the reference timing signal;
- and
- a re-timing circuit arranged to:
- receive the at least one frequency-divided signal;
- receive the 90° phase-shifted form of the reference timing signal;
- and
- re-time a set of transitions of the frequency-divided signal to be temporally aligned to transitions of the 90° phase-shifted form of the reference timing signal to generate the at least one timing signal comprising the re-timed transitions of the frequency-divided signal.
A method of generating a timing signal from a reference timing signal;
- the method comprising:
- generating a 90° phase-shifted form of the reference timing signal;
- generating at least one frequency-divided signal having a frequency equal to 1/M times the frequency of the reference timing signal, where M is an odd-numbered integer greater than 1;
- and
- re-timing a set of transitions of the frequency-divided signal to be temporally aligned to transitions of the 90° phase-shifted form of the reference timing signal to generate the timing signal comprising the re-timed transitions of the frequency-divided signal.
Dependencies are inferred from the claim text.