System and method for monitoring voltage across isolation barrier

A method of monitoring a voltage level in an isolated manner, the method comprising:

• receiving a first pulse-width modulation (PWM) signal that transitions between low and high levels at a first time;
• upon an expiration of a first time delay subsequent to the first time, performing an analog-to-digital conversion of a first input signal or first input value that is received, at least indirectly from a first terminal of a first transistor device, by a first input port of an analog-to-digital converter portion of a high voltage (HV) circuit portion of an isolation system so as to generate a result signal;
• upon receiving a request signal from a low voltage (LV) circuit portion of the isolation system at the HV circuit portion, sending the result signal or a further signal based upon the result signal across a galvanic barrier by way of a coupling channel to the LV circuit portion;
• determining one or both of a duty cycle and a frequency of a second PWM signal to be output from the LV circuit portion for receipt by another device, wherein the second PWM signal is based upon the result signal and indicative of the first input signal or first input value;
• and
• sending the second PWM signal for receipt by the other device,
• wherein, due to the galvanic barrier, the second PWM signal can be provided for receipt by the other device in a manner that avoids exposure of the other device to an undesirably high current or power level associated with the HV circuit portion or the first transistor device.

A control system for a high-power device, the control system comprising:

• a controller configured to transmit and receive low voltage signals;
• an integrated circuit coupled to the controller, the integrated circuit comprising:
• a first low voltage (LV) circuit portion including a first control logic portion;
• a first high voltage (HV) circuit portion including a second control logic portion and an analog-to-digital converter portion;
• and
• one or more coupling channels coupling the first LV and HV circuit portions by way of a galvanic barrier;
• and
• a first transistor device having a first terminal coupled at least indirectly to a first connection having a first voltage level and a second terminal coupled at least indirectly to a second connection having a second voltage level related to the first voltage level,
• wherein the second terminal is coupled at least indirectly to a first port of the analog-to-digital converter portion,
• wherein the first control logic portion governs provision of an output signal from an output terminal of the integrated circuit for receipt by the controller, the output signal being generated based at least indirectly upon the second voltage level and being indicative of the first voltage level, and
• wherein, due to the galvanic barrier, the output signal can be provided for receipt by the controller in a manner that avoids exposure of the other device to an undesirably high current or power level associated with the first HV circuit portion or the first transistor device.