Communications receiver equalizer

A communications receiver equalizer comprising:

• a first delay cell configured to receive a first voltage signal and output a second voltage signal delayed in time with respect to the first voltage signal;
• a second delay cell configured to receive the second voltage signal and output a third voltage signal delayed in time with respect to the second voltage signal;
• a first tap multiplier configured to multiply the second voltage signal by a first equalization coefficient for output as a multiplied second voltage signal;
• a second tap multiplier configured to multiply the third voltage signal by a second equalization coefficient for output as a multiplied third voltage signal;
• and
• a summation circuit configured to sum the multiplied second voltage signal with the multiplied third voltage signal to produce an equalized output signal,
• wherein the first and second delay cells each comprise:
• a transconductance stage configured to convert the first voltage signal to an output current signal, wherein the transconductance stage comprises:
• a pair of first and second transistors coupled in a source degeneration configuration;
• a negative resistance network coupled in parallel with a tunable resistor network;
• and
• shunt inductive circuitry coupled in parallel with the negative resistance network;
• and
• a transimpedance stage configured to convert the output current signal received from the transconductance stage to an output voltage signal, wherein the transimpedance stage comprises a first transimpedance amplifier coupled in series with a first shunt inductive circuit.

A data processing system comprising:

• a processor;
• a memory subsystem coupled to the processor;
• and
• a peripheral device coupled to the processor via a serial communications channel, wherein the peripheral device further comprises a communications receiver equalizer comprising:
• a first delay cell configured to receive a first voltage signal from the serial communications channel and output a second voltage signal delayed in time with respect to the first voltage signal;
• a second delay cell configured to receive the second voltage signal and output a third voltage signal delayed in time with respect to the second voltage signal;
• a first tap multiplier configured to multiply the second voltage signal by a first equalization coefficient for output as a multiplied second voltage signal;
• a second tap multiplier configured to multiply the third voltage signal by a second equalization coefficient for output as a multiplied third voltage signal;
• and
• a summation circuit configured to sum the multiplied second voltage signal with the multiplied third voltage signal to produce an equalized output signal, wherein the equalized output signal is an equalized version of the first voltage signal,
• wherein the first and second delay cells each comprise:
• a transconductance stage configured to convert the first voltage signal to an output current signal, wherein the transconductance stage comprises:
• a differential pair of first and second transistors coupled in a source degeneration configuration;
• a negative resistance network coupled in parallel with a tunable resistor network;
• and
• shunt inductive circuitry coupled in parallel with the negative resistance network;
• and
• a transimpedance stage configured to convert the output current signal received from the transconductance stage to an output voltage signal, wherein the transimpedance stage comprises a first transimpedance amplifier coupled in series with a first shunt inductive circuit.