Systems and methods for random number generation using a fractional rate clock

Abstract

Systems and methods are provided for generating a pseudo-random bit sequence at an output frequency using a clock signal operating at a first frequency that is lower than the output frequency. A first bit sequence of a particular type is generated using a clock signal operating at a first frequency. A second bit sequence is generated using the clock signal operating at the first frequency, where the second bit sequence is a delayed version of the first bit sequence. A delayed version of the first bit sequence is generated using the second bit sequence and another bit sequence, wherein the delayed version is delayed based on the particular type and a difference between the output frequency and the first frequency. The first bit sequence and the delayed version are combined to generate a pseudo-random bit sequence at the output frequency.

Dependencies are inferred from the claim text.