Semiconductor memory device and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunmin Lee, Changseok Kang, Jongwon Kim, Hyeong Park
Life of this patent
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Abstract
Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. The vertical channel structures penetrate the stack structure. Conductive pads are disposed on the vertical channel structures. An etch stopper covers sidewalls of the conductive pads. Pad contacts are disposed on the conductive pads to be in contact with the conductive pads. The pad contacts are further in contact with the etch stopper.
Claims20
A semiconductor memory device, comprising:
- stack structures arranged in a first direction, each of the stack structures including insulating layers and gate electrodes that are alternately and repeatedly stacked on a substrate;
- vertical channel structures each penetrating a corresponding one of the stack structures;
- conductive pads in contact with the vertical channel structures, each of the conductive pads disposed on a corresponding one of the vertical channel structures;
- and
- an etch stopper covering sidewalls of the conductive pads, exposing top surfaces of the conductive pads, and formed on a top surface of an uppermost insulating layer of the insulating layers of the stack structures,
- wherein the etch stopper is an isolated pattern on a corresponding one of the stack structures.
A semiconductor memory device, comprising:
- stack structures arranged in a first direction, each of the stack structures including insulating layers and gate electrodes that are alternately and repeatedly stacked on a substrate;
- vertical channel structures each penetrating a corresponding one of the stack structures;
- conductive pads in contact with the vertical channel structures, each of the conductive pads disposed on a corresponding one of the vertical channel structures;
- and
- a trench extending in a second direction crossing the first direction between adjacent ones of the stack structures;
- a common source plug in the trench;
- and
- an etch stopper on each of the stack structures, each etch stopper being an isolated pattern horizontally spaced apart from the trench, covering a portion of the conductive pads in the first and second directions, and formed on a top surface of an uppermost insulating layer of the insulating layers of the corresponding one of the stack structures.
A device, comprising:
- stack structures formed on a semiconductor substrate, the stack structures each including insulating layers and gate electrodes alternately and repeatedly stacked on the semiconductor substrate;
- vertical channel structures penetrating the stack structures, each stack structure being penetrated by at least two of the vertical channel structures;
- conductive pads each disposed on a corresponding one of the vertical channel structures;
- pad contacts each overlying and contacting a corresponding one of the conductive pads;
- and
- etch stoppers each disposed on a corresponding one of the stack structures and covering sidewalls of the conductive pads on the corresponding one of the stack structures, and formed on a top surface of an uppermost insulating layer of the insulating layers of the corresponding one of the stack structures,
- wherein adjacent ones of the etch stoppers are spaced apart from each other, and for each of the etch stoppers, the etch stopper extends from the corresponding conductive pads such that a perimeter of the etch stopper in plan view is disposed offset from outer conductive pads of the corresponding conductive pads by a distance.
Dependencies are inferred from the claim text.