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US 9,543,296 B2Granted
ESD clamp with auto biasing under high injection conditions
AssigneeNational Semiconductor Corporation
InventorVladislav Vashchenko
Life of this patent
Estimating the term…
Abstract
In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions.
Claims9
A dual direction ESD protection circuit, comprising:
- a first NPN bipolar junction transistor (BJT) having first base, a first emitter and a first collector;
- a second NPN bipolar junction transistor (BJT) having second base, a second emitter and a second collector, wherein the first collector and the second collector are connected together;
- a first diode having a first anode and a first cathode;
- a second diode having a second anode and a second cathode;
- first and second resistors, wherein the first and second resistors are in addition to the first base and the second base;
- a voltage pad and a ground pad;
- wherein the voltage pad is coupled to the first emitter, the first anode and the first base through the first resistor;
- wherein the ground pad is coupled to the second emitter, the second anode and the second base through the second resistor;
- wherein the first cathode and the second cathode are coupled to the first collector and the second collector;
- wherein the dual direction ESD protection circuit is configured to have bipolar SCR (BSCR) characteristics;
- wherein the dual direction ESD protection circuit is embodied in a semiconductor structure;
- a p-type substrate;
- an n-buried layer (NBL) touching the top surface of the p-type substrate;
- an n-type epitaxial layer touching the top surface of the NBL layer,
- wherein the n-type epitaxial layer forms the first and second collectors of the first and second NPN bipolar junction transistors respectively and the first and second cathodes of the first and second diodes respectively;
- a plurality of selective SiGe epitaxial regions touching the top surface of the n-type epitaxial layer, configured to define the first and second bases of the first and second NPN bipolar junction transistors respectively;
- a plurality of n-type emitter regions touching the tops of each of the selective SiGe epitaxial regions, thereby forming the first and second emitters of the first and second NPN bipolar junction transistors respectively;
- a plurality of P+ regions formed in the top surface of the n-type epitaxial layer, configured to define the first and second anodes of the first and second diodes respectively;
- and
- wherein the plurality of selective SiGe epitaxial regions are spaced apart from each other and the plurality of P+ regions are spaced apart from each other and each of the plurality of selective SiGe epitaxial regions.
17 more elements
A dual direction ESD protection circuit disposed in a p-type substrate, comprising:
- an n-buried layer (NBL) directly on the p-type substrate;
- an n-type layer directly on the NBL layer, wherein a shared region of the n-type layer forms a first collector of a first NPN bipolar junction transistor, a second collector of a second NPN bipolar junction transistor, a first cathode of a first diode, and a second cathode of a second diode;
- a plurality of SiGe regions directly on the n-type layer, the plurality of SiGe regions forming a first base of the first NPN bipolar junction transistor and a second base of the second NPN bipolar junction transistor;
- a plurality of n-type emitter regions directly on each of the SiGe regions, thereby forming a first emitter of the first NPN bipolar junction transistor and a second emitter of the second NPN bipolar junction transistor;
- a plurality of P+ regions in the shared region of the n-type layer to form a first anode of the first diode and a second anode of the second diode;
- a voltage pad and a ground pad;
- a first resistor connected between the SiGe region of the first base and the voltage pad, wherein the voltage pad is coupled to the first emitter and the first anode;
- a second resistor connected between the SiGe region of the second base and the ground pad, wherein the ground pad is coupled to the second emitter and the second anode;
- and
- wherein the plurality of SiGe regions are spaced apart from each other and the plurality of P+ regions are spaced apart from each other and each of the plurality of SiGe regions.
7 more elements
A dual direction ESD protection circuit disposed in a p-type substrate, comprising:
- an n-buried layer (NBL) directly on the p-type substrate;
- an n-type layer directly on the NBL layer, wherein a shared region of the n-type layer forms a first collector of a first NPN bipolar junction transistor, a second collector of a second NPN bipolar junction transistor, a first cathode of a first diode, and a second cathode of a second diode;
- a plurality of SiGe regions directly on the n-type layer, the plurality of SiGe regions forming a first base of the first NPN bipolar junction transistor and a second base of the second NPN bipolar junction transistor;
- a plurality of n-type emitter regions directly on each of the SiGe regions, thereby forming a first emitter of the first NPN bipolar junction transistor and a second emitter of the second NPN bipolar junction transistor;
- a plurality of P+ regions in the shared region of the n-type layer to form a first anode of the first diode and a second anode of the second diode;
- and
- wherein the plurality of SiGe regions are spaced apart from each other and the plurality of P+ regions are spaced apart from each other and each of the plurality of SiGe regions.
4 more elements
Dependencies are inferred from the claim text.