Integrated device comprising a matrix of OLED active pixels with improved dynamic range

A device, comprising:

• a semiconductor substrate having first and second parts electrically insulated from one another;
• and
• a matrix of active pixels formed in the semiconductor substrate and comprising, for each active pixel:
• an OLED diode having an anode, and
• a control circuit comprising:
• a first nMOS transistor having a gate, a body, and a source, the source of the first transistor being coupled to body of the first transistor and to the anode of the OLED diode, and
• a refresh circuit comprising a second nMOS transistor coupled to control the gate of the first nMOS transistor;
• wherein the first nMOS transistor is formed in the first part of the semiconductor substrate;
• wherein the refresh circuit is formed in the second part of the semiconductor substrate.

A device, comprising:

• a semiconductor substrate having first and second parts electrically insulated from one another;
• and
• a matrix of active pixels formed in the semiconductor substrate and comprising, for each active pixel:
• an OLED diode having an anode, and
• a control circuit comprising:
• a first nMOS transistor formed in the first part of the semiconductor substrate and having a gate, a body, and a source, the source of the first nMOS transistor being coupled to body of the first nMOS transistor and to the anode of the OLED diode, and
• a refresh circuit formed in the second part of the semiconductor substrate and being coupled to the gate of the first nMOS transistor, the refresh circuit comprising:
• a second nMOS transistor having a gate, a body, a source, and a drain, with the gate of the second nMOS transistor being coupled to a pixel row selection line, and the body of the second nMOS transistor being coupled to a first supply voltage, and
• a pMOS transistor having a gate, a body, a source, and a drain, with the gate of the pMOS transistor being coupled to a complement of the pixel row selection line, and the body of the pMOS transistor being coupled to a second supply voltage,
• wherein the source and drain of the second nMOS transistor are coupled respectively to the source and drain of the pMOS transistor.