Synchronization circuitry, common public radio interface enable device, and a method of synchronizing a synchronized clock signal of a second transceiver to a clock of a first transceiver

A controller device for a data interface between a slave sub-system and a master sub-system in a chain of at least two sub-systems in a mobile communication base station system, each of the sub-systems comprising at least one slave sub-system and at least one master sub-system for controlling the time of the slave sub-system, the at least one master sub-systems comprising a synchronization master sub-system controlling a time synchronization of the chain to an external clock external to the chain, the controller device comprising:

• a slave transceiver, for receiving a received signal representing binary data from a master sub-system, the binary data having a bit duration controlled by a clock cycle of a transmit clock of the master sub-system, and the transmitting data to the master sub-system, the transceiver being connected with a clock input to a controllable phase locked loop, PLL, for clocking the transceiver with the transmit clock;
• and
• a synchronization device for synchronizing the transmit clock of the slave transceiver to a clock of a master transceiver of the master sub-system based on the received signal received from the master sub-system, the synchronization circuitry comprising:
• a clock input port for receiving an external clock signal from an external clock generator;
• a received signal input port for receiving the received signal from the master transceiver;
• said PLL, for generating the transmit clock, the PLL comprising a PLL output for outputting the transmit clock, a first phase input coupled to the clock input port and a second phase input coupled to the PLL output via a negative feedback loop for providing a negative feedback signal;
• and
• a frequency and phase tracking loop coupling the received signal input and the second phase input, for providing a selection signal which controls a phase and/or frequency of the negative feedback signal to counter phase and or frequency error between the external clock signal and the received signal,
• wherein the frequency and phase tracking loop comprises:
• a clock recovery circuit for generating a receiver clock signal on basis of the transmit clock signal and the received signal,
• a phase detector circuit for generating a phase error signal, the phase detector circuit receiving the negative feedback signal and the receiver clock signal of which the frequency is divided by a first factor, the phase error signal indicating a phase difference between the negative feedback signal and the divided receiver clock signal,
• a selection signal generator for generating the selection signal on basis of the phase error signal, to select the selected clock signal, wherein the selection signal generator comprises an integrator and counter circuit for generating the selection signal.