Readout circuitry for image sensor

An image sensor comprising:

• an array of image sensor pixels;
• and
• readout circuitry having an array of readout units, wherein each readout unit includes:
• a plurality of analog-to-digital converters (“ADCs”) coupled to readout analog image signals from integer number m of two-dimensional blocks of pixels in the array of image sensor pixels;
• a plurality of blocks of Static Random-Access Memory (“SRAM”) coupled to receive digital image signals from the ADCs, wherein the digital image signals are representative of the analog image signals readout from the two-dimensional block of pixels, and wherein a quantity of the plurality of blocks of SRAM also numbering the integer number m;
• and
• a plurality of blocks of Dynamic Random-Access Memory (“DRAM”) coupled to the blocks of SRAM, the plurality of blocks of DRAM also numbering the integer number m, each block of SRAM coupled to sequentially output the digital image signals to each of the blocks of DRAM, wherein each of the readout units are coupled to output the digital image signals as a plurality of Input/Output (“IO”) signals, a quantity of the IO signals also numbering the integer number m.

Readout circuitry to readout an array of image sensor pixels, the readout circuitry comprising:

• readout units, wherein each readout unit includes:
• a plurality of analog-to-digital converters (“ADCs”) coupled to readout analog image signals from integer number m of two-dimensional blocks of the array of image sensor pixels;
• a plurality of blocks of Static Random-Access Memory (“SRAM”) coupled to receive digital image signals from the ADCs, wherein the digital image signals are representative of the analog image signal readout from the two-dimensional block of pixels, and wherein a quantity of the plurality of blocks of SRAM also numbering the integer number m;
• and
• a plurality of blocks of Dynamic Random-Access Memory (“DRAM”) coupled to the blocks of SRAM, the plurality of blocks of DRAM also numbering the integer number m, each block of SRAM coupled to sequentially output the digital image signals to each of the blocks of DRAM, wherein each of the readout units are coupled to output the digital image signals as a plurality of Input/Output (“IO”) signals, a quantity of the IO signals also numbering the integer number m.