Interconnected ring network in a multi-processor system

A method comprising:

• communicating by ones of a plurality of processing cores with a respective core interface module of a plurality of core interface modules, the plurality of core interface modules being configured as a first ring network, wherein ones of the plurality of core interface modules are coupled to a corresponding cache of a plurality of caches;
• receiving, by a first core interface module of the plurality of core interface modules from a first processing core of the plurality of processing cores, a transaction request to read data;
• checking, by the first core interface module, if the data to be read is cached in a first cache that is coupled to the first core interface module;
• and
• in response to the data not being cached in the first cache, simultaneously transmitting, by the first core interface module, (i) a first request to a second core interface module to check if the data to be read is cached in a second cache that is coupled to the second core interface module and (ii) a second request to a third core interface module to check if the data to be read is cached in a third cache that is coupled to the third core interface module, wherein simultaneously transmitting the first request and the second request further comprises:
• determining that the data to be read is associated with a first memory address of a memory,
• determining that a fourth core interface module is a home interface module for the first memory address of the memory,
• in response to (i) the data not being cached in the first cache and (ii) determining that the fourth core interface module is the home interface module for the first memory address of the memory, transmitting the transaction request to the fourth core interface module to check if the data to be read is cached in a fourth cache coupled to the fourth core interface module, and
• in response to the data not being cached in the fourth cache, simultaneously transmitting, by the first core interface module, (i) the first request to the second core interface module and (ii) the second request to the third core interface module.

A system comprising:

• a plurality of processing cores;
• and
• a plurality of core interface modules, ones of the plurality of processing cores coupled to a respective core interface module of the plurality of core interface modules, wherein ones of the plurality of core interface modules is associated with a respective cache of a plurality of caches, wherein a first core interface module of the plurality of core interface modules is coupled to a corresponding first processing core of the plurality of processing cores, wherein the plurality of core interface modules is configured as a first ring network,
• wherein the first core interface module is configured to
• receive, from the first processing core, a transaction request to read first data, wherein the first data to be read is associated with a first memory address of a memory, and wherein a second core interface module is a home interface module for the first memory address of the memory,
• check to determine if the first data to be read is cached in a first cache that is coupled to the first core interface module,
• in response to (i) the first data not being cached in the first cache and (ii) the second core interface module being the home interface module for the first memory address, transmit the transaction request to the second core interface module to check if the first data to be read is cached in a second cache coupled to the second core interface module,
• in response to the first data not being cached in the second cache, simultaneously transmit (i) a first request to a third core interface module to check if the first data to be read is cached in a third cache that is coupled to the third core interface module and (ii) a second request to a fourth core interface module to check if the first data to be read is cached in a fourth cache that is coupled to the fourth core interface module, wherein the first request and the second request are transmitted by the first core interface module without knowing, by the first core interface module, if the first data is respectively cached in the third cache and the fourth cache.

A system comprising:

• a plurality of processing cores;
• and
• a plurality of core interface modules, ones of the plurality of processing cores coupled to a respective core interface module of the plurality of core interface modules, wherein ones of the plurality of core interface modules is associated with a respective cache of a plurality of caches, wherein a first core interface module of the plurality of core interface modules is coupled to a corresponding first processing core of the plurality of processing cores, wherein the plurality of core interface modules is configured as a first ring network,
• wherein the first core interface module is configured to
• receive, from the first processing core, a transaction request to read data,
• check to determine if the data to be read is cached in a first cache that is coupled to the first core interface module, and
• in response to the data not being cached in the first cache, simultaneously transmit (i) a first request to a second core interface module to check if the data to be read is cached in a second cache that is coupled to the second core interface module and (ii) a second request to a third core interface module to check if the data to be read is cached in a third cache that is coupled to the third core interface module, wherein the first core interface module is configured to simultaneously transmit the first request and the second request by:
• determining that the data to be read is associated with a first memory address of a memory,
• determining that a fourth core interface module is a home interface module for the first memory address of the memory,
• in response to (i) the data not being cached in the first cache and (ii) determining that the fourth core interface module is the home interface module for the first memory address of the memory, transmitting the transaction request to the fourth core interface module to check if the data to be read is cached in a fourth cache coupled to the fourth core interface module, and
• in response to the data not being cached in the fourth cache, simultaneously transmitting, by the first core interface module, (i) the first request to the second core interface module and (ii) the second request to the third core interface module.