Memory controller, memory system, and memory control method
AssigneeKabushiki Kaisha Toshiba
InventorsRiki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
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AssigneeKabushiki Kaisha Toshiba
InventorsRiki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
Estimating the term…
According to one embodiment, a memory controller includes a writing destination management unit which determines a writing destination of user data, an encoding unit which generates a parity of the user data, and an ECC management unit which measures a fatigue degree of each certain memory area of a nonvolatile memory, selects an encoding method to instruct the encoding unit to be performed according to the encoding method, and changes the encoding method to an encoding method having a high error correction capability in a case where the fatigue degree corresponding to the writing destination is equal to or higher than a threshold and a total sum of parities is equal to or less than a predetermined amount.
A memory controller that controls a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, comprising:
A memory controller that controls a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, comprising:
A memory controller that controls a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, comprising:
Dependencies are inferred from the claim text.