Architecture for ensuring monotonicity in a digital-to-analog converter

A digital-to-analog converter (DAC) configured to convert a digital word input having J bits to an analog signal, the DAC comprising:

• 2J current sources, in which each of the 2J current sources is configured to produce a current having a value I0;
• an output node;
• a current divider having a programmable divide ratio, D, where 1/D is between 0 and 1;
• a first switch configured to selectively couple 2J−1 of the 2J current sources to the output node, in which one of the 2J current sources is not coupled to the output node;
• and
• a second switch configured to selectively couple each of the 2J current sources to the current divider.

A method of dividing a current with a programmable current mirror having K bits, the method comprising:

• coupling a current source, producing a current, I0, to the current mirror, the current mirror having a first transistor and a second transistor, each transistor having a source, the source of the first transistor being electrically coupled to the source of the second transistor, the first transistor having a programmable gain, the second transistor having a programmable gain;
• configuring the programmable gain of the first transistor to a value N, where N is greater than or equal to 1;
• configuring the programmable gain of the second transistor to a value M, where M=2K−N;
• and
• outputting a divided current from the programmable current mirror, the divided current being I0×(M/(N+M)).