Digital to analog converter, unit for the same, and method for using the same
AssigneeGwangju Institute of Science and Technology
InventorsMin-Jae Lee, Seong-Geon Kim, Jae-Hyun Kang
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Abstract
Disclosed herein is a digital-to-analog converter (DAC) including a clock driver for controlling a clock signal to provide an inverse delay clock signal to allow at least selective adjustment of a return to zero (RZ) section; and a DAC core comprising at least two DAC units for receiving a digital input value, the clock signal and the inverse delay clock signal and providing an analog output value. According to the present invention, distortion of the output of the DAC may be attenuated and loss of the output may be minimized by utilizing the RZ technique.
Claims15
A digital-to-analog converter (DAC) comprising:
- a clock driver for controlling a clock signal to provide an inverse delay clock signal to allow at least selective adjustment of a return to zero (RZ) section;
- and
- a DAC core comprising at least two DAC units for receiving a digital input value, the clock signal and the inverse delay clock signal and providing an analog output value.
A digital-to-analog converter (DAC) unit comprising:
- a return to zero (RZ) flip-flop for receiving a clock signal and an inverse delay clock signal delayed by an RZ section by converting the clock signal and outputting 0 as a flip-flop output signal and an inverse flip-flop output signal in the RZ section;
- a switch driver for outputting 0 as a reset signal when both the flip-flop output signal and the inverse flip-flop output signal are 0;
- and
- an output unit for outputting an output value of 0 in a section having the reset signal equal to 0 and outputting a positive or negative output value in a section having the reset signal unequal to 0.
A method of operating a digital-to-analog converter (DAC) comprising a clock driver and a DAC core, the method comprising:
- controlling, by the clock driver, a clock signal to provide an inverse delay clock signal for allow at least selective adjustment of a return to zero (RZ) section;
- receiving, by the DAC core comprising at least two DAC units, the clock signal, the inverse delay clock signal, and a digital input value;
- adjusting, by the DAC core, the RZ section based on the received clock signal and the received inverse delay clock signal;
- and
- converting, by the DAC core, the digital input value based on the adjusted RZ section to output an analog output value.
Dependencies are inferred from the claim text.