Successive approximation register converter

A method for performing an analog-to-digital conversion by means of a successive approximation register analog-to-digital converter (SAR ADC), the method comprising:

• performing, by a first comparison stage, a first set of decision steps;
• adjusting, by a regulation circuit, a common mode of a input signal towards a target common mode;
• performing, by a second comparison stage, a second set of decision steps;
• wherein the adjusting of the common mode is executed before the performing of the second set of decision steps.

A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a successive approximation analog-to-digital converter (SAR ADC) configured to provide a digital approximation of a sampled input signal as a result of a successive approximation operation, the SAR ADC comprising:
• a first comparison stage configured to perform a first set of decision steps of the successive approximation operation;
• a second comparison stage configured to perform a second set of decision steps of the successive approximation operation;
• and
• a regulation circuit configured to adjust a common mode of a input signal towards a target common mode before the second comparison stage performs the second set of decision steps.