Digital phase locked loop (PLL) system with frequency band jump in lock mode

A phase locked loop (PLL) control system, comprising:

• a digital controlled oscillator (DCO) comprising:
• a delay cell chain comprising a number (B) of delay cells;
• and
• a load control cell comprising a number (L) of load cells;
• a frequency-band jump controller module configured to:
• receive a second clock signal, a feedback clock signal, a lead/lag detection result that indicates whether the feedback clock signal leads or lags the second clock signal, a first digital control signal, and a second digital control signal;
• when a value (L) of the first digital control signal has reached a minimum value and has continued to decrease, or when the value (L) of the first digital control signal has reached a maximum value and has continued to increase:
• generate a frequency band jump signal to transition the DCO from operating in a lock mode to operating in a frequency-band jump mode;
• and
• a DCO control signal generator configured to:
• process the second clock signal, the lead/lag detection result and the frequency band jump signal to dynamically adjust:
• the value (L) of the first digital control signal to control the number (L) of load cells that are switched on to control an amount of delay in the DCO, and
• a value (B) of the second digital control signal to control the number (B) of delay cells that are active and part of the delay cell chain.