Phase lock loop with dynamic lock ranges

A phase lock loop (PLL) circuit, comprising:

• a voltage control oscillator (VCO) configured to receive a control voltage and generate an adjusted oscillation signal having a target frequency adjustable by the control voltage;
• a frequency divider coupled with the VCO to receive the adjusted oscillation signal, the frequency divider configured to generate a feedback oscillation signal by reducing the target frequency;
• a detector circuit coupled between the frequency divider and the VCO, the detector circuit configured to detect a difference between the feedback oscillation signal and a reference oscillation signal, and configured to generate the control voltage based on the difference;
• and
• a calibration circuit coupled with the detector circuit, the calibration circuit configured to receive a temperature reading corresponding to a junction temperature of the PLL circuit, the calibration circuit configured to preset the control voltage based on the temperature reading during a calibration procedure of the PLL circuit.

A method for calibrating a phase lock loop (PLL) device, the method comprising:

• receiving, by a calibration circuit, a temperature reading corresponding to a junction temperature of the PLL device;
• determining, by the calibration circuit, an initial control voltage by applying the temperature reading to a function corresponding to a detector circuit of the PLL device and a range of ambient temperatures within which the PLL circuit operates;
• and
• generating, by the detector circuit, the initial control voltage for biasing a voltage control oscillator (VCO) of the PLL device.