Frequency detection circuit and reception circuit

A reception circuit comprising:

• a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value corresponding to a center value of an amplitude level of input data, and the input data at first timing of a first clock;
• a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value, and the input data at the first timing;
• a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock having a phase shifted from that of the first clock;
• a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas based on the first comparison result, the second comparison result, and the third comparison result;
• a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector so as to determine whether a second frequency of the first clock or the second clock is higher or lower with respect to a first frequency of the input data;
• a fourth comparison circuit configured to output a fourth comparison result produced by comparison between the input data and the first threshold value at the first timing;
• a phase control unit configured to detect a phase difference between the input data, and the first clock or the second clock based on the third comparison result and the fourth comparison result;
• and
• a clock generation unit configured to generate the first clock and the second clock based on the phase difference and the rotation direction.

A reception circuit comprising:

• a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value corresponding to a center value of an amplitude level of input data, and the input data at first timing of a first clock;
• a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value, and the input data at the first timing;
• a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock having a phase shifted from that of the first clock;
• a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas based on the first comparison result, the second comparison result, and the third comparison result;
• a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector so as to determine whether a second frequency of the first clock or the second clock is higher or lower with respect to a first frequency of the input data;
• a selection unit configured to select either the first comparison result or the second comparison result as a first data determination result based on a second data determination result before the one-bit width time;
• a phase control unit configured to detect a phase difference between the input data, and the first clock or the second clock based on the third comparison result and the first data determination result;
• and
• a clock generation unit configured to generate the first clock and the second clock based on the phase difference and the rotation direction.