Apparatus and method for detecting or repairing minimum delay errors

An apparatus comprising:

• a clock circuit to receive a first clock signal with a first frequency and to output a second clock signal, wherein the clock circuit is to output the second clock signal with the first frequency in a normal operation mode, and wherein the clock circuit is to output the second clock signal with a second frequency in a minimum-delay debug mode, wherein the second frequency in the minimum-delay debug mode is lower than the first frequency in the normal operation mode;
• and
• a minimum-delay error detector (MDED), coupled to the clock circuit, to receive a data signal from a data path, to receive the second clock signal, and to detect a minimum-delay error (MDE) in the data path based on the received data signal and the second clock signal in the minimum-delay debug mode, wherein the MDED comprises a dual-edge triggered flip-flop, and wherein the dual-edge triggered flip-flop comprises a transparent-on-high latch, a transparent-on-low latch, and an output multiplexer, the transparent-on-high latch and the transparent-on-low latch to receive the data signal at respective clock terminals and to receive the second clock signal at respective data terminals.