Power gating and clock gating in wiring levels

A semiconductor system comprising:

• a first logical processing unit (LPU) integrated in a front end of line portion transmitting an electrical signal, in response to a first operation being performed be the first LPU, via an enable wire to a power gate and a clock gate, the power gate and the clock gate are integrated into one or more wiring levels of a plurality of wiring levels of a back end of line (BEOL) portion;
• the power gate and the clock gate activating a power grid and a clock net, respectively;
• the enable wire transmitting an electrical signal to a latch of a second LPU once the power grid and the clock net are activated;
• a signal wire transmitting an electrical signal, in response to the first operation being performed, to the latch;
• and
• the second LPU being activated to perform a second operation in response to the latch receiving the electrical signal from the signal wire and the enable wire.