Duty cycle detection and correction circuit in an integrated circuit

A method of generating clock signals, comprising:

• generating by a first driver cell a first output clock signal based on a first clock signal and a set of control signals;
• generating by the first driver cell a second output clock signal based on a second clock signal and the set of control signals, the first clock signal and the second clock signal having a predetermined phase difference;
• determining a duty cycle of the first output clock signal based on the first output clock signal and the second output clock signal;
• adjusting the set of control signals according to the duty cycle of the first output clock signal;
• and
• generating by a second driver cell a third output clock signal based on the first clock signal and the set of control signals.

A clock generating circuit, the circuit comprising:

• a first clock tree configured to receive a first clock signal and a second clock signal, to generate a first output clock signal based on the first clock signal and a set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals, the first clock signal and the second clock signal having a first predetermined phase difference;
• a second clock tree configured to receive a third clock signal and to generate a third output clock signal based on the first clock signal and the third clock signal and the set of control signals, the third clock signal and the first clock signal having a second predetermined phase difference;
• and
• a duty cycle correction circuit configured to receive the first output clock signal and the second output clock signal and to generate the set of control signals based on the first output clock signal and the second output clock signal.