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AssigneeQUALCOMM Incorporated
InventorsLior Amarilio, Alexander Golubitski, Haim Hagay Haller, Felix Kolmakov, Gilad Sthoeger
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Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.
A delay circuit for delaying an output enable signal, comprising:
A method for delaying an output enable signal, comprising:
A delay circuit for delaying an output enable, comprising:
A system comprising:
Dependencies are inferred from the claim text.