Delay structure for a memory interface

An apparatus for delaying a signal, comprising:

• means for receiving a first rising edge at an input;
• means for enabling an oscillator in response to receiving the first rising edge;
• means for counting a number of oscillations of the oscillator;
• means for outputting a second rising edge at an output if the number of oscillations reaches a predetermined number;
• and
• means for disabling the oscillator until a third rising edge is received at the input in response to the number of oscillations reaching the predetermined number.

A delay device, comprising:

• a first delay stage, the first delay stage comprising:
• a first oscillator;
• and
• a first count circuit having an input and an output, wherein the first count circuit is configured to transition the output of the first count circuit from a high logic state to a low logic state in response to receiving a first rising edge at the input of the first count circuit, to count a number of oscillations of the first oscillator in response to receiving a the first rising edge at the input of the first count circuit, and to output a second rising edge at the output of the first count circuit if the number of oscillations of the first oscillator reaches a first predetermined number;
• and
• a second delay stage, the second delay stage comprising:
• a second oscillator;
• and
• a second count circuit having an input coupled to the output of the first count circuit and an output, wherein the second count circuit is configured to receive the transition from the high logic state to the low logic state at the input of the second count circuit, to count a number of oscillations of the second oscillator in response to receiving the second rising edge at the input of the second count circuit, and to output a third rising edge at the output of the second count circuit if the number of oscillations of the second oscillator reaches a second predetermined number.