Rail-to-rail constant transconductance differential input stage

A differential input apparatus, comprising:

• a tail-connected primary differential pair of transistors, first and second transistors of the primary differential pair current channel coupled in series with first and second loads, respectively, to receive first and second input signals at first and second gates, respectively, of the primary differential pair of transistors and to pass load current to the first and second loads responsive to the first and second input signals;
• a tail-connected secondary differential pair of transistors, first and second transistors of the secondary differential pair current channel-coupled in series with the first and second loads, respectively, to receive downward level-shifted versions of the first and second input signals at first and second gates, respectively, of the secondary differential pair of transistors, the secondary differential pair to conduct current responsive to the downward level-shifted versions of the differential input signals as the primary differential pair of transistors approaches a cut-off condition such as to present a constant transconductance to the first and second loads as a common-mode component of the first and second input signals approaches a positive voltage rail;
• a tail current source transistor communicatively coupled between a positive voltage rail and current channels associated with the primary and secondary differential pairs to provide tail current to the primary and secondary differential pairs;
• and
• a tail current shunt transistor channel-coupled in series between the tail current source transistor current channel and the current channels of the first and second transistors of the secondary differential pair, the tail current shunt transistor to supply tail current to the secondary differential pair as the primary differential pair approaches the cut-off condition.

A method of providing a constant-transconductance electronic differential input stage, comprising:

• receiving a first input signal approaching a positive voltage rail at a first gate associated with a first transistor of a tail-connected primary differential pair of transistors;
• receiving a second input signal approaching the positive voltage rail at a second gate associated with a second transistor of the tail-connected primary differential pair of transistors;
• decreasing current flow from a tail current source transistor through the primary differential pair, resulting in an increased voltage potential at a tail node associated with the primary differential pair;
• providing a tail current to first and second transistors associated with a secondary differential pair of transistors in order to maintain a constant first transconductance in series with a first load associated with the first transistors of the primary and secondary differential pairs and to maintain a constant second transconductance in series with a second load associated with the second transistors of the primary and secondary differential pairs as a common-mode component of the first and second input signals approaches the positive voltage rail;
• receiving the first input signal approaching the positive voltage rail at a gate of a first source-follower transistor output-coupled to a gate of the first transistor of the secondary differential pair;
• receiving the second input signal approaching the positive voltage rail at a gate of a second source-follower transistor output-coupled to a gate of the second transistor of the secondary differential pair;
• and
• conducting current through the first source-follower transistor, resulting in a decreased voltage at a positive terminal of a current channel associated with the first source-follower transistor and a bias toward conduction at a gate of a tail current shunt transistor gate-coupled to the positive terminal of the current channel associated with the first source-follower transistor and channel-coupled in series between a current channel of the tail current source transistor and current channels of the first and second transistors associated with the secondary differential pair.

A differential input apparatus, comprising:

• a tail-connected primary differential pair to receive first and second input signals and to pass load current to first and second loads responsive to the first and second input signals, respectively;
• a tail-connected secondary differential pair to receive downward level-shifted versions of the first and second input signals;
• and
• a tail current shunt device in series between a tail current source and the secondary differential pair.