Control method and control system of three level inverter
AssigneeFuji Electric Co., Ltd.
InventorIkuya Sato
Life of this patent
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Abstract
A three-phase inverter includes three-level inverters connected in parallel to one another, each being capable of outputting a DC high voltage, DC middle voltage, and DC low voltage. A method for controlling the three-phase inverter produces on-time ratios in one switching period of switching elements in the three-level inverters, so as to make the three-phase inverter for one phase alternately output the DC high voltage and the DC middle voltage, to make the three-phase inverter for another phase output the DC middle voltage, and to make the three-phase inverter for the remaining phase alternately output the DC middle voltage and the DC low voltage.
Claims12
A method for controlling a three-phase inverter that is connected to a DC power source having a high voltage DC terminal, a middle voltage DC terminal, and a low voltage DC terminal, wherein the three-phase inverter has a plurality of output terminals and includes three three-level inverters that are connected to the DC power source in parallel with one another and that have semiconductor switching elements, at least one of the semiconductor switching elements being connected between the high voltage DC terminal and one of the output terminals of the three-phase inverter, at least one of the semiconductor switching elements being connected between the middle voltage DC terminal and said one of the output terminals, and at least one of the semiconductor switching elements being connected between the low voltage DC terminal and said one of the output terminals, wherein the method makes the switching elements in the three-level inverters turn on and off on the basis of output voltage commands during a sequence of time periods to thereby generate three-phase AC voltages at the output terminals of the three-phase inverter, the method comprising:
- (A) obtaining on-time ratios for the semiconductor switching elements in each of the three-level inverters on the basis of the output voltage commands;
- (B) dividing the output voltage commands during a time period into a plurality of sections, wherein the time period is defined as a duration of one alternating current cycle of the output voltage commands;
- and
- (C) during each of the sections of the output voltage commands,
- in the three-level inverter for one of the phases, generating switching control signals to make at least one of the semiconductor switching elements that is connected between the high voltage DC terminal and said one of the output terminals to turn on and off alternately based on a respective on-time ratio, and additionally generating switching control signals to make at least one of the semiconductor switching elements that is connected between the middle voltage DC terminal and said one of the output terminals to alternately turn on and off based on a respective on-time ratio,
- in the three-level inverter for another of the phases, generating a switching control signal to turn on at least one semiconductor switching element that is connected between the middle voltage DC terminal and the output terminal regardless of the on-time ratios;
- and
- in the three-level inverter for the remaining phase, generating switching control signals to make at least one of the semiconductor switching elements that is connected between the middle voltage DC terminal and said one of the output terminals alternately turn on and off based on a respective on-time ratio, and additionally generating switching control signals to make at least one semiconductor switching element that is connected between the low voltage DC terminal and said one of the output terminals alternately turn on and off based on a respective on-time ratio.
A method for controlling a three-phase inverter that is connected to a DC power source having a high voltage DC terminal, a middle voltage DC terminal, and a low voltage DC terminal, wherein the three-phase inverter has a plurality of output terminals and includes three three-level inverters that are connected to the DC power source in parallel with one another and that have semiconductor switching elements, at least one of the semiconductor switching elements being connected between the high voltage DC terminal and one of the output terminals of the three-phase inverter, at least one of the semiconductor switching elements being connected between the middle voltage DC terminal and said one of the output terminals, and at least one of the semiconductor switching elements being connected between the low voltage DC terminal and said one of the output terminals, wherein the method makes the switching elements in the three-level inverters turn on and off on the basis of output voltage commands during a sequence of time periods to thereby generate three-phase AC voltages at the output terminals of the three-phase inverter, the method comprising:
- (A) obtaining on-time ratios for the semiconductor switching elements in each of the three-level inverters on the basis of the output voltage commands;
- (B) dividing the output voltage commands during a time period into a plurality of sections wherein the time period is defined as a duration of one alternating current cycle of the output voltage commands;
- and
- (C) during each of the sections of the output voltage commands,
- in the three-level inverter for one of the phases, controlling one of the semiconductor switching elements that is connected between the high voltage DC terminal and said one of the output terminals and the at least one of the semiconductor switching elements that is connected between the low voltage DC terminal and said one of the output terminals to be in a turned-on state regardless of the on-time ratios to output one of the voltage at the high voltage DC terminal and the low voltage DC terminal,
- in the three-level inverter for another of the phases, generating switching control signals to make at least one of the semiconductor switching elements that is connected between the high voltage DC terminal and said one of the output terminals alternately turn on and off based on a respective on-time ratio, and additionally generating switching control signals to make at least one semiconductor switching element that is connected between the low voltage DC terminal and said one of the output terminals alternately turn on and off based on a respective on-time ratio,
- in the three-level inverter for the remaining phase, when the three-level inverter for another phase outputs the voltage at the high voltage DC terminal to said one of the output terminals, generating switching control signals to make at least one of the semiconductor switching elements that is connected between the low voltage DC terminal and said one of the output terminals turn on and off based on a respective on-time ratio, and additionally generating switching control signals to make at least one semiconductor switching element that is connected between the middle voltage DC terminal and said one of the output terminals alternately turn on and off based on a respective on-time ratio to alternately output the voltage at the low voltage DC terminal and the voltage at the middle voltage DC terminal, and
- in the three-level inverter for said remaining phase, when the three-level inverter for another phase outputs the voltage at the low voltage DC terminal to said one of the output terminals, generating switching control signals to make at least one of the semiconductor switching elements that is connected between the high voltage DC terminal and said one of the output terminals alternately turn on and off based on a respective on-time ratio, and additionally generating switching control signals to make at least one semiconductor switching element that is connected between the middle voltage DC terminal and said one of the output terminals alternately turn on and off based on a respective on-time ratio to alternately output the voltage at the high voltage DC terminal and the voltage at the middle voltage DC terminal.
Dependencies are inferred from the claim text.