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US 9,520,559 B2Granted
Heterojunction oxide non-volatile memory device
Assignee4D-S Pty, Ltd
InventorDongmin Chen
Life of this patent
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Abstract
A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.
Claims15
A method, comprising:
- providing a plurality of switching devices, the switching devices arranged in an array of bitlines and wordlines, wherein each switching device comprises a first memory device which yields a clock wise current to a voltage hysteresis loop and a second memory device coupled to the first memory device, wherein the second memory device, yields a counter clock wise current to the voltage hysteresis loop;
- and
- addressing a selected switching device within the array of bitlines and wordlines, wherein the selected switching device is located within a selected bitline and a selected wordline, wherein the addressing comprises:
- applying a selected wordline voltage;
- applying a selected bitline voltage;
- applying an unselected wordline voltage to wordlines not selected;
- and
- applying an unselected bitline voltage to bitlines not selected.
5 more elements
Dependencies are inferred from the claim text.