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US 9,520,557 B2Granted
Silicon based nanoscale crossbar memory
AssigneeThe Regents of the University of Michigan
InventorsWei Lu, Sung Hyun Jo, Kuk-Hwan Kim
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Abstract
The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.
Claims20
A semiconductor device comprising:
- a semiconductor substrate;
- a first array of electrodes disposed above the semiconductor substrate, wherein the first array of electrodes comprise a first metal-containing material, wherein the first metal is selected from a group consisting of:
- aluminum, nickel, platinum and tungsten;
- a second array of electrodes disposed above the first array of electrodes, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein the second array of electrodes comprises a second metal-containing material;
- and
- a plurality of resistive switching nanostructures disposed between the first array of electrodes and the second array of electrodes, wherein each resistive switching nanostructure provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites;
- and
- wherein particles of the first metal derived from the first metal-containing material are diffused within defect sites of at least one resistive switching nanostructure from the plurality of resistive switching nanostructures, and wherein the particles of the first metal form a conductive filament within the one resistive switching nanostructure.
5 more elements
A method for fabricating a semiconductor device comprising:
- receiving a semiconductor substrate;
- forming a first array of electrodes above the semiconductor substrate, wherein the first array of electrodes comprises a first metal-containing material;
- forming a plurality of resistive switching nanostructures above the first array of electrodes, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites;
- and
- forming a second array of electrodes above the plurality of resistive switching nanostructures, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein each resistive switching nanostructure from the plurality of resistive switching nanostructures provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the second array of electrodes comprise a second metal-containing material, and wherein the second metal is selected from a group consisting of:
- aluminum, nickel, platinum and tungsten;
- wherein particles of the second metal from the second metal-containing material are configured to diffuse within defect sites of at least one resistive switching nanostructure from the plurality of resistive switching nanostructures to thereby form a conductive filament within the one resistive switching nanostructure.
4 more elements
A method for operating a semiconductor device comprising a semiconductor substrate comprises:
- applying a first voltage across a first electrode from a first array of electrodes and a first electrode from a second array of electrodes through a resistive switching nanostructure of a plurality of resistive switching nanostructures, to thereby induce a first current flow between the first electrode from the second array of electrodes and the first electrode from the first array of electrodes, wherein the first array of electrodes are disposed above the semiconductor substrate, wherein the first array of electrodes comprises a first metal-containing material, a plurality of resistive switching nanostructures above the first array of electrodes, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites, and wherein the second array of electrodes are disposed above the plurality of resistive switching nanostructures, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein each resistive switching nanostructure from the plurality of resistive switching nanostructures provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the second array of electrodes comprise a second metal-containing material, and wherein the second metal is selected from a group consisting of:
- aluminum, nickel, platinum and tungsten;
- and
- determining a first resistance state of the resistive switching nanostructure in response to the first current flow.
1 more element
Dependencies are inferred from the claim text.