Self heating reduction for analog radio frequency (RF) device

A method for forming a semiconductor device, comprising:

• epitaxially growing a first lower semiconductor layer on a top surface of a first region of a bulk semiconductor substrate;
• epitaxially growing a first upper semiconductor layer on a top surface of the first lower semiconductor layer located on the first region of the bulk semiconductor substrate to form a first region first intermediate structure;
• etching the first upper semiconductor layer to form a first plurality of semiconductor fins spaced apart from each other on the top surface of the first lower semiconductor layer to transform the first region first intermediate structure into a first region second intermediate structure;
• forming a first shallow trench isolation (STI) trench and a second STI trench on opposing sides of the first region second intermediate structure as one another to transform the first region second intermediate structure into a first region third intermediate structure;
• forming a plurality of first region gate structures straddling over a portion of each of the first plurality of semiconductor fins at a location in between a first end and a second end of each of the first plurality of semiconductor fins of the first region third intermediate structure to transform the first region third intermediate structure into a first region fourth intermediate structure;
• partially etching the first lower semiconductor layer from the first region fourth intermediate structure to form a first region space beneath the first plurality of semiconductor fins and beneath the plurality of first region gate structures, and to form at least one vertical pillar formed of the remaining unetched portions of the first region first semiconductor layer located in a portion of the first region space to transform the first region fourth intermediate structure into a first region fifth intermediate structure, and wherein the at least one vertical pillar has a same height as the first region space and contacts a top surface of the first region of the bulk semiconductor substrate and a bottom surface of the first plurality of semiconductor fins;
• and
• forming a first spacer layer including a dielectric material on sidewalls of the plurality of first region gate structures and filling in the first region space of the first region fifth intermediate structure such that a portion of the first spacer layer located in the first region space laterally surrounds the at least one vertical pillar and partially isolates the second region of the bulk semiconductor substrate from the second plurality of semiconductor fins and the second region gate structures, and the at least one vertical pillar provides a heat dissipation path from the first region gate structures and the first plurality of semiconductor fins to the first region of the bulk semiconductor substrate.

A method of forming a semiconductor device comprising:

• etching a first upper semiconductor layer of a first structure comprising a bulk semiconductor substrate, a first lower semiconductor layer located on a top surface of a first region of the bulk semiconductor substrate, and the first upper semiconductor layer located on a top surface of the first lower semiconductor layer to form a first plurality of semiconductor fins spaced apart from each other on the top surface of the first lower semiconductor layer;
• forming at least one first region gate structure straddling over a portion of the first plurality of semiconductor fins at a location between a first end and a second end of the first plurality of semiconductor fins;
• removing the first lower semiconductor layer from the first structure except for a portion of the first lower semiconductor layer located beneath a portion of at least one of the first plurality of semiconductor fins that is overlapped by the at least one first region gate structure to form a first region space in the first structure, and wherein the remaining unetched portion of the first lower semiconductor layer contacts the bulk semiconductor substrate and at least one of the first plurality of semiconductor fins;
• and
• depositing a first dielectric layer on the first structure filling in the first region space, and wherein the first dielectric layer laterally surrounds the remaining unetched portion of the first lower semiconductor layer in the first region space such that the at least one first region gate structure and the first plurality of semiconductor fins are partially isolated from the first region of the bulk semiconductor substrate, wherein the bulk semiconductor substrate of the first structure includes silicon, the first lower semiconductor layer includes one of silicon germanium (SiGe) or indium phosphide (InP), and the first upper semiconductor layer includes one of silicon or indium arsenide (InAs), and wherein the bulk semiconductor substrate further includes a second region, and the method further comprises:
• etching a second upper semiconductor layer of a second structure comprising the second region of the bulk semiconductor substrate, a second lower semiconductor layer located on a top surface of the second region of the bulk semiconductor substrate, and the second upper semiconductor layer located on a top surface of the second lower semiconductor layer to form a second plurality of semiconductor fins spaced apart from each other on the top surface of the second lower semiconductor layer;
• forming at least one second region gate structure straddling over a portion of the second plurality of semiconductor fins at a location between a first end and a second end of the second plurality of semiconductor fins;
• removing the entire second lower semiconductor layer from the second structure to form a second region space between a top surface of the second region of the bulk semiconductor substrate and a bottom surface of the second plurality of semiconductor fins and a bottom surface of the at least one second region gate structure;
• and
• depositing a second dielectric layer on the second intermediate structure filling in the entire second region space such that the second plurality of semiconductor fins and the at least one second gate structure are fully isolated from the second region of the bulk semiconductor substrate by the second dielectric layer, and
• wherein a width of the at least one second region gate structure is less than a width of the at least one first region gate structure.