Semiconductor devices including a stressor in a recess and methods of forming the same

A semiconductor device comprising:

• a substrate;
• a gate structure including a gate dielectric layer over the substrate and a gate electrode over the gate dielectric layer;
• a spacer adjacent to a sidewall of the gate electrode;
• and
• a semiconductor layer disposed adjacent to the gate structure and disposed in a recess that extends below an upper surface of the substrate, the semiconductor layer being a strain-inducing pattern,
• wherein a portion of the recess underlies the gate structure,
• wherein the spacer directly contacts a first portion of the semiconductor layer above a lower surface of the gate dielectric layer,
• wherein the semiconductor layer comprises a second portion in the substrate, and the second portion of the semiconductor layer comprises a first sidewall that directly contacts the upper surface of the substrate and has a linear shape and a second sidewall that directly contacts the first sidewall and has a linear shape,
• wherein the first and second sidewalls of the second portion of the semiconductor layer are slanted with respect to the upper surface of the substrate and converge at a convergence interface, and
• wherein the gate electrode overlaps the convergence interface.

A method for forming a semiconductor device, the method comprising:

• forming a gate structure over a semiconductor substrate, the gate structure including a gate insulating layer and a gate electrode over the gate insulating layer;
• forming a first spacer over the semiconductor substrate;
• forming a second spacer along a sidewall of the gate structure;
• forming a recess extending into the semiconductor substrate adjacent to the gate structure, wherein the recess comprises a notched portion of the semiconductor substrate that underlies the gate structure and is spaced apart from the gate structure, the notched portion comprises a first sidewall directly contacting an upper surface of the semiconductor substrate and a second sidewall directly contacting the first sidewall of the recess, each of the first and second sidewalls has a linear shape, and the gate electrode overlaps a portion of the recess;
• removing at least a portion of the first spacer;
• and
• filling the recess with a stressor that directly contacts a bottom surface of the first spacer,
• wherein a contacting interface between the stressor and the bottom surface of the first spacer is not below a lower surface of the gate insulating layer, and
• the stressor is a strain-inducing pattern.

A semiconductor device comprising:

• a substrate;
• a gate structure disposed on the substrate;
• a spacer adjacent to a sidewall of the gate structure;
• and
• a semiconductor layer disposed adjacent to the gate structure and disposed in a recess that extends below an upper surface of the substrate, the semiconductor layer being a strain-inducing pattern,
• wherein a portion of the recess underlies the gate structure, and
• wherein an interface between the spacer and the semiconductor layer located under the spacer is coplanar with a lower surface of the gate structure,
• wherein the semiconductor layer in the substrate comprises a first portion contacting the spacer and a second portion below the first portion,
• wherein the first portion comprises a first sidewall having a linear shape and has a width gradually increasing with a depth of the recess, and the second portion comprises a second sidewall having a linear shape and has a width gradually decreasing with the depth of the recess.