Vertical non-planar semiconductor device for system-on-chip (SoC) applications

An N-type vertical fin-FET device, comprising:

• a silicon fin disposed on a bulk silicon substrate, the silicon fin having a recessed portion and an uppermost portion;
• a source region disposed in the recessed portion of the silicon fin;
• a drain region disposed in the uppermost portion of the silicon fin;
• an N-type gate electrode disposed over the uppermost portion of the silicon fin, between the source and drain regions;
• and
• a substantially vertical channel region disposed between the source and drain regions and electrically controlled by the N-type gate electrode.

A method of fabricating a semiconductor device, the method comprising:

• forming a semiconductor fin above a substrate;
• forming a subdoping region of a first conductivity type in the bottom of the semiconductor fin;
• forming an upper doping region of the first conductivity type in the top of the semiconductor fin, the upper doping region separated from the subdoping region;
• forming a gate electrode over the semiconductor fin;
• etching the semiconductor fin to provide a recessed portion and an uppermost portion of the semiconductor fin;
• forming a source region in the recessed portion of the semiconductor fin, the source region comprising at least a portion of the subdoping region;
• and
• forming a drain region in the uppermost portion of the semiconductor fin, the drain region comprising at least a portion of the upper doping region, wherein the gate electrode is between the source and drain regions.