3D independent double gate flash memory on bounded conductor layer

A memory device, comprising:

• a plurality of word line layers, a word line layer in the plurality including a first word line structure comprising a first landing pad element and a plurality of even word lines extending away from the first landing pad element, and a second word line structure comprising a second landing pad element and a plurality of odd word lines extending away from the second landing pad element and interdigitated with the plurality of even word lines;
• a plurality of rows of active pillars and insulating pillars extending through the plurality of word line layers, the rows in the plurality disposed between corresponding even word lines and odd word lines, the active pillars in a row in the plurality of rows comprising respectively a vertical channel structure, a charge storage layer and an outside insulating layer;
• the insulating pillars in the row separating the even and odd word lines between the active pillars;
• and
• a bounded conductive layer configured as a common source of reference potential for the plurality of rows of active pillars, below and in electrical communication with the active pillars in the plurality of rows of active pillars.