Compact ReRAM based PFGA

A method for fabricating a push-pull resistive random access memory cell circuit for an integrated circuit on a semiconductor substrate, the method comprising:

• forming active regions for first and second programming transistors and for at least one switch transistor in the semiconductor substrate and forming source and drain regions in the active regions for first and second programming transistors defining channels for the first and second programming transistors such that the first and second programming transistors have a pitch length and a channel length respectively equal to the pitch length and channel length of logic transistors formed in the integrated circuit;
• forming source and drain regions defining a channel for the at least one switch transistor in the active region for at least one switch transistor;
• forming gates for the first and second programming transistors over the channels for the first and second programming transistors, the gates for the first and second programming transistors both having a same thickness;
• forming a gate for the at least one switch transistor over the channel for the at least one switch transistor;
• forming contacts to each of the source and gate of the first programming transistor, to the drain and gate of the second programming transistor, and to the gate of the at least one switch transistor;
• forming from a first segment of a first level metal interconnect line a source word line for the push-pull resistive random access memory cell circuit, the first segment of the first metal interconnect line connected to the contact to the source of the first programming transistor;
• forming from a second segment of the first level metal interconnect line a word line for the push-pull resistive random access memory cell circuit, the second segment of the first metal interconnect line connected to the contacts to the gates of the first and second programming transistors;
• forming from a third segment of the first level metal interconnect line an interconnect conductor connected to the contacts to the drain of the second programming transistor and the gate of the at least one switch transistor;
• forming a fourth segment of the first level metal interconnect line;
• forming a first resistive random access memory device over the third segment of the first level metal interconnect line;
• forming a second resistive random access memory device over the fourth segment of the first level metal interconnect line;
• forming contacts to each of the first and second resistive random access memory devices, to the third segment of the first metal interconnect layer, and to the fourth segment of the first level metal interconnect line;
• forming from a first segment of a second level metal interconnect line a bit line for the push-pull resistive random access memory cell circuit connected to the contact to the second resistive random access memory device;
• forming from a second segment of the second level metal interconnect line a complementary bit line for the push-pull resistive random access memory cell circuit connected to the contact to the first resistive random access memory device;
• and
• forming a third segment of the second level metal interconnect line connected to the contacts to the third segment of the first metal interconnect layer and the first resistive random access memory device.